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Subversion Repositories vga_lcd

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Rev Log message Author Age Path
64 Added old uploaded documents to new repository. root 5539d 20h /
63 Added old uploaded documents to new repository. root 5540d 01h /
62 New directory structure. root 5540d 01h /
61 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7534d 22h /
60 all WB outputs are registered, but just when we dont use cursors markom 7534d 22h /
59 Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors. rherveille 7567d 04h /
58 Enabled Fifo Underrun test rherveille 7567d 04h /
57 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme.
2) Changed top level and pixel generator to reflect changes in the fifo.
3) Changed a bug in vga_fifo.
4) Changed pixel generator and wishbone master to reflect changes.		 rherveille 7588d 00h /
56 Removed 'or negedge arst' from sluint/luint sensitivity list rherveille 7616d 20h /
55 Initial release. rherveille 7673d 21h /
54 Added DVI tests rherveille 7673d 21h /
53 Fixed some Wishbone RevB.3 related bugs.
Changed layout of the core. Blocks are located more logically now.
Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.		 rherveille 7674d 02h /
52 Numerous updates and added checks rherveille 7674d 02h /
51 Forgot to change document revision number rherveille 7721d 20h /
50 Forgot to change document revision rherveille 7721d 20h /
49 Added WISHBONE revB.3 signals rherveille 7721d 21h /
48 WISHBONE revB.3 signals added rherveille 7721d 21h /
47 Added wb_b3_check
Removed ud_cnt, ro_cnt		 rherveille 7722d 18h /
46 Added WISHBONE revB.3 sanity checks rherveille 7722d 18h /
45 Changed timing generator; made it smaller and easier. rherveille 7722d 23h /
44 Changed timing section in VGA core, changed testbench accordingly.
Fixed bug in 'timing check' test.		 rherveille 7722d 23h /
43 Added WISHBONE revB.3 Registered Feedback Cycles support rherveille 7723d 14h /
42 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8056d 00h /
41 specs version 1.1 rherveille 8056d 00h /
40 no message rherveille 8056d 00h /
39 Changed video timing generator.
Changed wishbone master vertical gate count code.
Fixed a potential bug in the wishbone slave (cursor color register readout).		 rherveille 8056d 02h /
38 Changed testbench to reflect modified VGA timing generator. rherveille 8056d 02h /
37 Fixed a potential reset bug in the hint & vint generation. rherveille 8071d 05h /
36 Fixed two small bugs that only showed up when the hardware cursors were disabled rherveille 8079d 07h /
35 no message rherveille 8079d 10h /

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