| Rev |
Log message |
Author |
Age |
Path |
| 47 |
Deleted all files, the repository was moved to Nikhef Gitlab, files will come back to OpenCores when it supports git. |
fransschreuder |
980d 10h |
/ |
| 46 |
New Vivado version, changed regmap clock, added byte enable to regmap
* Updated wupper for Vivado 2018.1
* Byte enable on registermap is now supported
* Fixed i2c mux reset (inversion) on VC709 board
* Regmap is now running on 25 MHz for better timing, this was 41.6 MHz
* registers can now be disabled at build time using the generate statement in the .yaml file |
fransschreuder |
1827d 08h |
/ |
| 45 |
Fixed duplicate driver and Vivado 2018.1 PCIe core |
fransschreuder |
1851d 16h |
/ |
| 44 |
EDITED: added image size |
aborga |
1939d 08h |
/ |
| 43 |
ADDED: README.md to be parsed by the OC project page |
aborga |
1939d 13h |
/ |
| 42 |
Added filter in wuppercodegen in order to generate 2d arrays of registers |
fransschreuder |
2284d 13h |
/ |
| 41 |
Added brief description of Wishbone |
broel |
2384d 12h |
/ |
| 40 |
Updated comment header for syscon. |
broel |
2384d 14h |
/ |
| 39 |
Added Wishbone bus to Wupper plus a Wishbone memory as an example. |
broel |
2388d 09h |
/ |
| 38 |
Fixed include of stdint.h |
broel |
2396d 15h |
/ |
| 37 |
* Added WupperCodeGen, a tool to generate the registermap vhdl, c++ and latex doc from a single .YAML file
* Fixed bug: crash when polling enable bits while transferring DMA in two directions at the same time
* Code cleanup
* Updated documentation with WupperCodeGen |
fransschreuder |
2397d 08h |
/ |
| 36 |
Updated documentation |
fransschreuder |
2732d 09h |
/ |
| 35 |
FIXED:
* PCIe lock when reading registers on a high frequency
* Added threshold registers for Prog Full of the FromHost fifo
* Code cleanup |
fransschreuder |
2786d 13h |
/ |
| 34 |
FIXED:
* Wrong TLP length reported on register writes
* Two simultaneous interrupts were not handled
* XADC wizard for ultrascale devices
Added:
* Added voltage (int, aux, bram) readout on XADC wizards |
fransschreuder |
2892d 08h |
/ |
| 33 |
ADDED:
-- supportedtools.tex, again to test the OC repo |
aborga |
2937d 07h |
/ |
| 32 |
MODIFIED:
-- minor things just to test OC svn repo |
aborga |
2937d 07h |
/ |
| 31 |
Added example application documentation. |
oussamak |
3031d 09h |
/ |
| 30 |
Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools |
oussamak |
3031d 10h |
/ |
| 29 |
Improved application to reflect both up and down transfers |
fransschreuder |
3073d 07h |
/ |
| 28 |
Added registermap reset |
fransschreuder |
3073d 09h |
/ |
| 27 |
Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path
Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming |
fransschreuder |
3073d 12h |
/ |
| 26 |
Added sys_clk constraint |
fransschreuder |
3073d 15h |
/ |
| 25 |
Added scripts and constraints for KCU105 |
fransschreuder |
3073d 15h |
/ |
| 24 |
Added:
* Support for KCU105 board in code
TODO
* Add constraints and build scripts for KCU105 |
fransschreuder |
3074d 08h |
/ |
| 23 |
Fixed reset of application registers |
fransschreuder |
3131d 14h |
/ |
| 22 |
Added dma_soft_reset to trigger register resets |
fransschreuder |
3137d 14h |
/ |
| 21 |
Fixed BUG http://opencores.org/bug,view,2562 |
fransschreuder |
3146d 11h |
/ |
| 20 |
Fixed:
* Missing packets if the fifo goes empty during a TLP
* Dynamically change the empty threshold of the main fifo to TLP size |
fransschreuder |
3160d 09h |
/ |
| 19 |
* driver/README updated |
oussamak |
3166d 11h |
/ |
| 18 |
Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register |
oussamak |
3166d 13h |
/ |
