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URL https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk

Subversion Repositories wb_lpc

[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] - Rev 20

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Rev Log message Author Age Path
20 New directory structure. root 5526d 00h /wb_lpc/trunk/rtl/verilog/
19 Serirq: incorrect stop frame:
* The stop frame should be two clocks for quiet mode and three for continuous mode.		 hharte 5598d 15h /wb_lpc/trunk/rtl/verilog/
17 Fix bugs:
25-Jul-2008 LPC firmware writes must not insert wait-states.
22-Jul-2008 LPC DMA does not report READY+MORE for multi-byte transfers

Add feature:
23-Jul-2008 propagate Wishbone errors across LPC interface

Improve Testbench:
Ability to test multiple wait-states on LPC Peripheral Wishbone Master interface.
Check wbs_err_o from LPC Host.

Rebuild examples with the fixes above.		 hharte 5752d 15h /wb_lpc/trunk/rtl/verilog/
15 fixed bug: Spec vviolation for multi-byte firmware amcesses:
the multi-byte firmware accesses incorrectly follow the multi-byte DMA algorithm and issue a SYNC sequence between each byte transferred. Instead, multi-byte firmware accesses should issue a single SYNC sequence following the transfer of the multi-byte data phase		 hharte 5756d 21h /wb_lpc/trunk/rtl/verilog/
11 Add Serial IRQ Support hharte 5890d 20h /wb_lpc/trunk/rtl/verilog/
6 Clean up whitespace. hharte 5896d 04h /wb_lpc/trunk/rtl/verilog/
5 Fix bug in LPC Host that was causing a 2nd LPC cycle because the wishbone cycle was not completely retired when going back to the idle state.
Also clean up whitespace.		 hharte 5896d 04h /wb_lpc/trunk/rtl/verilog/
4 Adding .cvsignore files to ignore .svn directories. hharte 5898d 07h /wb_lpc/trunk/rtl/verilog/
3 Initial checkin of source files hharte 5898d 14h /wb_lpc/trunk/rtl/verilog/

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