URL https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk

Subversion Repositories wb_lpc

[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [wb_lpc_host.v] - Rev 20

Rev	Log message	Author	Age	Path
20	New directory structure.	root	5527d 23h	/wb_lpc/trunk/rtl/verilog/wb_lpc_host.v
17	Fix bugs: 25-Jul-2008 LPC firmware writes must not insert wait-states. 22-Jul-2008 LPC DMA does not report READY+MORE for multi-byte transfers Add feature: 23-Jul-2008 propagate Wishbone errors across LPC interface Improve Testbench: Ability to test multiple wait-states on LPC Peripheral Wishbone Master interface. Check wbs_err_o from LPC Host. Rebuild examples with the fixes above.	hharte	5754d 15h	/wb_lpc/trunk/rtl/verilog/wb_lpc_host.v
15	fixed bug: Spec vviolation for multi-byte firmware amcesses: the multi-byte firmware accesses incorrectly follow the multi-byte DMA algorithm and issue a SYNC sequence between each byte transferred. Instead, multi-byte firmware accesses should issue a single SYNC sequence following the transfer of the multi-byte data phase	hharte	5758d 20h	/wb_lpc/trunk/rtl/verilog/wb_lpc_host.v
5	Fix bug in LPC Host that was causing a 2nd LPC cycle because the wishbone cycle was not completely retired when going back to the idle state. Also clean up whitespace.	hharte	5898d 04h	/wb_lpc/trunk/rtl/verilog/wb_lpc_host.v
3	Initial checkin of source files	hharte	5900d 13h	/wb_lpc/trunk/rtl/verilog/wb_lpc_host.v