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[/] [wb_lpc/] [trunk/] [sim/] - Rev 20


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Rev Log message Author Age Path
20 New directory structure. root 3972d 15h /wb_lpc/trunk/sim/
17 Fix bugs:
25-Jul-2008 LPC firmware writes must not insert wait-states.
22-Jul-2008 LPC DMA does not report READY+MORE for multi-byte transfers

Add feature:
23-Jul-2008 propagate Wishbone errors across LPC interface

Improve Testbench:
Ability to test multiple wait-states on LPC Peripheral Wishbone Master interface.
Check wbs_err_o from LPC Host.

Rebuild examples with the fixes above.
hharte 4199d 06h /trunk/sim/
14 Update for Xilinx ISE 10.1 hharte 4203d 21h /trunk/sim/
13 Add testbench for serirq. hharte 4336d 21h /trunk/sim/
6 Clean up whitespace. hharte 4342d 19h /trunk/sim/
4 Adding .cvsignore files to ignore .svn directories. hharte 4344d 22h /trunk/sim/
3 Initial checkin of source files hharte 4345d 04h /trunk/sim/

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