| Rev |
Log message |
Author |
Age |
Path |
| 21 |
Added formal verification properties
This core now passes formal verification. |
dgisselq |
1713d 22h |
/ |
| 20 |
Made the bench/cpp Makefile independent of the Verilator root |
dgisselq |
2753d 13h |
/ |
| 19 |
Cleaned up the controller, corrected comments, tried to make it more readable. |
dgisselq |
2753d 14h |
/ |
| 18 |
We now pass all tests again--this time for a 4:1 controller, with a CAS of 5
and a CWL of 5. This is designed for a memory running at 320MHz,
transmitting across the data lines as 640Mbps, and yet running internally at
only 80MHz. |
dgisselq |
2784d 08h |
/ |
| 17 |
Here are files from my current attempts to include the DDR3 SDRAM into an
Arty project. Although a part of the Arty project, and not really sub modules
to anything here, they really belong with this project. |
dgisselq |
2808d 14h |
/ |
| 16 |
New, modified code, now works in simulation!! |
dgisselq |
2812d 13h |
/ |
| 15 |
Some simple timing diagrams, illustrating how we can go about this. |
dgisselq |
2815d 18h |
/ |
| 14 |
Lots of changes. Redesigned the refresh logic, and the activate/precharge
logic. While it's still not working on the hardware, it looks better than
before. (I also caught some bugs in the MRx register settings ...) |
dgisselq |
2828d 09h |
/ |
| 13 |
Cleanup, bug fixes--sadly, the code no longer works, so while it's "better"
in that it can build at 200MHz, it no longer works in the Verilator simulation. |
dgisselq |
2829d 08h |
/ |
| 12 |
Added the write-read and write-precharge extra delays into both module and
simulation. |
dgisselq |
2830d 13h |
/ |
| 11 |
Fixed the bugs Xilinx's tools pointed out. |
dgisselq |
2830d 14h |
/ |
| 10 |
This might just work ... at least, it passes my testbench. |
dgisselq |
2830d 15h |
/ |
| 9 |
Making progress: The singular write and pipe read tests work. Random pipe
reads still failing. |
dgisselq |
2830d 15h |
/ |
| 8 |
Singular reads and writes now work (in the Verilator simulator)--just not
pipelined reads or writes. |
dgisselq |
2831d 00h |
/ |
| 7 |
Make lots of progress. Reset works, and refresh is within a clock measurement
or two of working properly. Singular sequential writes work as well. |
dgisselq |
2832d 09h |
/ |
| 6 |
Lots of bug fixes. The controller now proceeds through the proper reset
logic into the first write. This includes activating the needed bank and the
next one, and then issuing the write command. It doesn't complete the write
command yet, but that's the next step. |
dgisselq |
2833d 09h |
/ |
| 5 |
Under Verilator/simulation testing, the core now properly brings the device
up from reset. Next step: opening/closing banks. |
dgisselq |
2833d 15h |
/ |
| 4 |
Work continues. A preliminary test-bench has been created. The core
has yet to pass through the reset cycle yet, so there's a lot of work
still to be done. |
dgisselq |
2834d 07h |
/ |
| 3 |
Fixes some, not all, of the Verilator build/lint errors. |
dgisselq |
2834d 23h |
/ |
| 2 |
Initial checkin. Pieces are not working yet, but the general approach is
starting to take shape. |
dgisselq |
2835d 00h |
/ |
