URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] - Rev 11

Rev	Log message	Author	Age	Path
11	Fixed the bugs Xilinx's tools pointed out.	dgisselq	2847d 14h	/wbddr3/
10	This might just work ... at least, it passes my testbench.	dgisselq	2847d 15h	/wbddr3/
9	Making progress: The singular write and pipe read tests work. Random pipe reads still failing.	dgisselq	2847d 16h	/wbddr3/
8	Singular reads and writes now work (in the Verilator simulator)--just not pipelined reads or writes.	dgisselq	2848d 00h	/wbddr3/
7	Make lots of progress. Reset works, and refresh is within a clock measurement or two of working properly. Singular sequential writes work as well.	dgisselq	2849d 10h	/wbddr3/
6	Lots of bug fixes. The controller now proceeds through the proper reset logic into the first write. This includes activating the needed bank and the next one, and then issuing the write command. It doesn't complete the write command yet, but that's the next step.	dgisselq	2850d 09h	/wbddr3/
5	Under Verilator/simulation testing, the core now properly brings the device up from reset. Next step: opening/closing banks.	dgisselq	2850d 16h	/wbddr3/
4	Work continues. A preliminary test-bench has been created. The core has yet to pass through the reset cycle yet, so there's a lot of work still to be done.	dgisselq	2851d 07h	/wbddr3/
3	Fixes some, not all, of the Verilator build/lint errors.	dgisselq	2851d 23h	/wbddr3/
2	Initial checkin. Pieces are not working yet, but the general approach is starting to take shape.	dgisselq	2852d 01h	/wbddr3/
1	The project and the structure was created	root	2852d 05h	/wbddr3/