URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdramsim.h] - Rev 12

Rev	Log message	Author	Age	Path
12	Added the write-read and write-precharge extra delays into both module and simulation.	dgisselq	2847d 16h	/wbddr3/trunk/bench/cpp/ddrsdramsim.h
6	Lots of bug fixes. The controller now proceeds through the proper reset logic into the first write. This includes activating the needed bank and the next one, and then issuing the write command. It doesn't complete the write command yet, but that's the next step.	dgisselq	2850d 12h	/wbddr3/trunk/bench/cpp/ddrsdramsim.h
4	Work continues. A preliminary test-bench has been created. The core has yet to pass through the reset cycle yet, so there's a lot of work still to be done.	dgisselq	2851d 10h	/wbddr3/trunk/bench/cpp/ddrsdramsim.h