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[/] [xulalx25soc/] [trunk/] [rtl/] - Rev 102

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Rev	Log message	Author	Age	Path
102	Updated documentation. The documentation for these now also reflects that these were drawn from an FPGA Library project, that is shared among many FPGA builds.	dgisselq	2861d 09h	/xulalx25soc/trunk/rtl/
101	Fixed the `defines at the top so that this can be built without any CPU. This was then used to measure the impact of the CPU on the entire build, as you could now build with no CPU, and then with a CPU to compare.	dgisselq	2861d 09h	/xulalx25soc/trunk/rtl/
100	Includes updates so this can run at higher clocks speeds within an FPGA.	dgisselq	2861d 10h	/xulalx25soc/trunk/rtl/
99	Includes high-speed updates. rxuart and txuart will now run at 200MHz on an Artix-7, so should not impact timing (any more) on the XuLA platform.	dgisselq	2861d 10h	/xulalx25soc/trunk/rtl/
98	Updated copyright notices for the new year, to reflect that changes have been made in 2016.	dgisselq	2861d 10h	/xulalx25soc/trunk/rtl/
90	Reads and writes to the SD over SPI port now work. The card appears, as of now, to be fully functional.	dgisselq	2884d 14h	/xulalx25soc/trunk/rtl/
89	Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic into one register, this fixes that logic so that instructions without their condition fulfilled are still "executed" and marked as done.	dgisselq	2884d 14h	/xulalx25soc/trunk/rtl/
88	Adjusted copyright date.	dgisselq	2884d 14h	/xulalx25soc/trunk/rtl/
87	Placed the interrupt into the carry chain for less logic area.	dgisselq	2884d 14h	/xulalx25soc/trunk/rtl/
86	Fine tuning the `defines, so that you can build pipelined without pipelined bus access and so forth.	dgisselq	2884d 14h	/xulalx25soc/trunk/rtl/
85	First version of the SD-SPI interface, with partial functionality. (No the empty link that was here before.)	dgisselq	2888d 11h	/xulalx25soc/trunk/rtl/
84	First part of switching to proper sdspi.v, and not just the link.	dgisselq	2888d 11h	/xulalx25soc/trunk/rtl/
83	Fixes a bug in the LX9 build whereby the flash was never ever granted permission to use the SPI port.	dgisselq	2889d 14h	/xulalx25soc/trunk/rtl/
74	Adds the SD-card capability, and connects the debug wires to/from the uartdev in case it needs to be debugged.	dgisselq	2890d 10h	/xulalx25soc/trunk/rtl/
73	Simplified logic.	dgisselq	2890d 10h	/xulalx25soc/trunk/rtl/
72	Sets XULA25 as the default.	dgisselq	2890d 10h	/xulalx25soc/trunk/rtl/
71	Needed to play with subtle timing to get this to build. Expect me to play with these two clock numbers more.	dgisselq	2890d 10h	/xulalx25soc/trunk/rtl/
70	Cosmetic (minor) update.	dgisselq	2890d 10h	/xulalx25soc/trunk/rtl/
69	Massive logic simplification. This is also the first (verified) working version.	dgisselq	2890d 10h	/xulalx25soc/trunk/rtl/
68	Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb. Fixed the multiply option parameter, so it sets a 3-clock multiply properly. Adjusted the watchdog timer so that it now produces a timer that doesn't reload--since this is pointless for a watchdog. Finally, connects a reset line to the DMA, to make certain that resetting the CPU will also reset any ongoing DMA operation.	dgisselq	2890d 10h	/xulalx25soc/trunk/rtl/

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Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] - Rev 102

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