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[/] [xulalx25soc/] [trunk/] [rtl/] [busmaster.v] - Rev 74

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74 Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged.		 dgisselq 2904d 10h /xulalx25soc/trunk/rtl/busmaster.v
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.		 dgisselq 2982d 14h /xulalx25soc/trunk/rtl/busmaster.v
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 2994d 12h /xulalx25soc/trunk/rtl/busmaster.v
18 Got the bitfile back up to speed at 80 MHz. dgisselq 3060d 13h /xulalx25soc/trunk/rtl/busmaster.v
9 Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz.		 dgisselq 3062d 11h /xulalx25soc/trunk/rtl/busmaster.v
6 Initial file load, likely to be buggy, but the initial load nonetheless. dgisselq 3065d 07h /xulalx25soc/trunk/rtl/busmaster.v
2 A very first, albeit incomplete, build. dgisselq 3065d 08h /xulalx25soc/trunk/rtl/busmaster.v

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