URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] - Rev 102

Rev	Log message	Author	Age	Path
31	A bug fix, although one that rearranges the bus. The first four I/O locations have been adjusted. The new locations are reflected in wishbone.html. In addition, the PWM and UART devices no longer create bus errors when accessed. Finally, this version uses a `define XULA25 to determine whether or not to build for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define would be to place it into your Xilinx configuration, should you wish to build for the LX25.	dgisselq	3003d 08h	/xulalx25soc/trunk/rtl/cpu/
26	Some bug fixes, and the long jump early branching integration.	dgisselq	3004d 09h	/xulalx25soc/trunk/rtl/cpu/
23	This fixes a bug in the early branching system, and clarifies that early branch instructions will not affect the flags. It's a basic bug fix update.	dgisselq	3012d 19h	/xulalx25soc/trunk/rtl/cpu/
21	Files, not links, to replace what were once broken links in this project.	dgisselq	3065d 18h	/xulalx25soc/trunk/rtl/cpu/
19	Step one in fixing soft link poblems. The following files were soft links, and not brought into the svn repository properly. They'll be replaced in the next update with their full sources.	dgisselq	3065d 18h	/xulalx25soc/trunk/rtl/cpu/
2	A very first, albeit incomplete, build.	dgisselq	3074d 04h	/xulalx25soc/trunk/rtl/cpu/