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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [cpuops.v] - Rev 118

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118 Lots of changes. The biggest are to the CPU: MPYxHI instructions are now
verified to be working, ILLegal instructions stop at the right location,
the STEP bit no longer self-clears, etc. Other changes cleaned up the
internal documentation and removed parameters that should only have local
scope from the global parameter list. The NEW_INSTRUCTION_SET was also
removed from the CPU, since ... it's been new for too long to really be new
anymore.		 dgisselq 2739d 08h /xulalx25soc/trunk/rtl/cpu/cpuops.v
113 Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache.		 dgisselq 2857d 01h /xulalx25soc/trunk/rtl/cpu/cpuops.v
60 LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively.		 dgisselq 2894d 20h /xulalx25soc/trunk/rtl/cpu/cpuops.v
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 2942d 20h /xulalx25soc/trunk/rtl/cpu/cpuops.v
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.		 dgisselq 2972d 23h /xulalx25soc/trunk/rtl/cpu/cpuops.v
21 Files, not links, to replace what were once broken links in this project. dgisselq 3047d 08h /xulalx25soc/trunk/rtl/cpu/cpuops.v

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