URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [div.v] - Rev 118

Rev	Log message	Author	Age	Path
118	Lots of changes. The biggest are to the CPU: MPYxHI instructions are now verified to be working, ILLegal instructions stop at the right location, the STEP bit no longer self-clears, etc. Other changes cleaned up the internal documentation and removed parameters that should only have local scope from the global parameter list. The NEW_INSTRUCTION_SET was also removed from the CPU, since ... it's been new for too long to really be new anymore.	dgisselq	2739d 08h	/xulalx25soc/trunk/rtl/cpu/div.v
113	Lots of updates, mostly focused on getting the XuLA board and CPU able to pass a comprehensive test suite. At this point, everything passes and logic usage is down even. Among the few changes includes the "break" bit in the uCC register, used to indicate a switch to supervisor mode occurred as a result of a user break, and the ability for the supervisor to clear the instruction cache.	dgisselq	2857d 01h	/xulalx25soc/trunk/rtl/cpu/div.v
98	Updated copyright notices for the new year, to reflect that changes have been made in 2016.	dgisselq	2865d 19h	/xulalx25soc/trunk/rtl/cpu/div.v
61	Fixed the timing control wires: busy and valid will never both be true. Busy will be true (now) until valid is asserted, and busy will never not be asserted until valid is true.	dgisselq	2894d 20h	/xulalx25soc/trunk/rtl/cpu/div.v
21	Files, not links, to replace what were once broken links in this project.	dgisselq	3047d 08h	/xulalx25soc/trunk/rtl/cpu/div.v