| Rev |
Log message |
Author |
Age |
Path |
| 118 |
Lots of changes. The biggest are to the CPU: MPYxHI instructions are now
verified to be working, ILLegal instructions stop at the right location,
the STEP bit no longer self-clears, etc. Other changes cleaned up the
internal documentation and removed parameters that should only have local
scope from the global parameter list. The NEW_INSTRUCTION_SET was also
removed from the CPU, since ... it's been new for too long to really be new
anymore. |
dgisselq |
2739d 16h |
/xulalx25soc/trunk/rtl/cpu/idecode.v |
| 113 |
Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache. |
dgisselq |
2857d 09h |
/xulalx25soc/trunk/rtl/cpu/idecode.v |
| 98 |
Updated copyright notices for the new year, to reflect that changes have been
made in 2016. |
dgisselq |
2866d 03h |
/xulalx25soc/trunk/rtl/cpu/idecode.v |
| 86 |
Fine tuning the `defines, so that you can build pipelined without pipelined
bus access and so forth. |
dgisselq |
2889d 07h |
/xulalx25soc/trunk/rtl/cpu/idecode.v |
| 62 |
Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated. |
dgisselq |
2895d 04h |
/xulalx25soc/trunk/rtl/cpu/idecode.v |
| 52 |
This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change. |
dgisselq |
2943d 05h |
/xulalx25soc/trunk/rtl/cpu/idecode.v |
| 51 |
Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags. |
dgisselq |
2953d 03h |
/xulalx25soc/trunk/rtl/cpu/idecode.v |
| 50 |
Updates to fix some broken early branching code, both in idecode and pfcache. |
dgisselq |
2962d 06h |
/xulalx25soc/trunk/rtl/cpu/idecode.v |
| 26 |
Some bug fixes, and the long jump early branching integration. |
dgisselq |
2986d 07h |
/xulalx25soc/trunk/rtl/cpu/idecode.v |
| 23 |
This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update. |
dgisselq |
2994d 17h |
/xulalx25soc/trunk/rtl/cpu/idecode.v |
| 21 |
Files, not links, to replace what were once broken links in this project. |
dgisselq |
3047d 16h |
/xulalx25soc/trunk/rtl/cpu/idecode.v |
