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[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [pfcache.v] - Rev 118

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118 Lots of changes. The biggest are to the CPU: MPYxHI instructions are now
verified to be working, ILLegal instructions stop at the right location,
the STEP bit no longer self-clears, etc. Other changes cleaned up the
internal documentation and removed parameters that should only have local
scope from the global parameter list. The NEW_INSTRUCTION_SET was also
removed from the CPU, since ... it's been new for too long to really be new
anymore.		 dgisselq 2739d 02h /xulalx25soc/trunk/rtl/cpu/pfcache.v
113 Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache.		 dgisselq 2856d 19h /xulalx25soc/trunk/rtl/cpu/pfcache.v
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.		 dgisselq 2952d 13h /xulalx25soc/trunk/rtl/cpu/pfcache.v
50 Updates to fix some broken early branching code, both in idecode and pfcache. dgisselq 2961d 16h /xulalx25soc/trunk/rtl/cpu/pfcache.v
21 Files, not links, to replace what were once broken links in this project. dgisselq 3047d 02h /xulalx25soc/trunk/rtl/cpu/pfcache.v

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