URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [pfcache.v] - Rev 113

Rev	Log message	Author	Age	Path
113	Lots of updates, mostly focused on getting the XuLA board and CPU able to pass a comprehensive test suite. At this point, everything passes and logic usage is down even. Among the few changes includes the "break" bit in the uCC register, used to indicate a switch to supervisor mode occurred as a result of a user break, and the ability for the supervisor to clear the instruction cache.	dgisselq	2861d 12h	/xulalx25soc/trunk/rtl/cpu/pfcache.v
51	Lots of bug fixes. The ugliest were in the prefetch cache, where instructions from one cache line were being issued as valid in another. Other fixes include pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the decode was adjusted so that brev no longer affects the flags.	dgisselq	2957d 06h	/xulalx25soc/trunk/rtl/cpu/pfcache.v
50	Updates to fix some broken early branching code, both in idecode and pfcache.	dgisselq	2966d 08h	/xulalx25soc/trunk/rtl/cpu/pfcache.v
21	Files, not links, to replace what were once broken links in this project.	dgisselq	3051d 19h	/xulalx25soc/trunk/rtl/cpu/pfcache.v