OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [zipcpu.v] - Rev 117

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
117 Updates, to include new README and bench/cpp/Makefile that doesnt depend upon
a static VERILATOR_ROOT location.		 dgisselq 2768d 08h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
113 Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache.		 dgisselq 2861d 09h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
98 Updated copyright notices for the new year, to reflect that changes have been
made in 2016.		 dgisselq 2870d 04h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
89 Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic
into one register, this fixes that logic so that instructions without their
condition fulfilled are still "executed" and marked as done.		 dgisselq 2893d 08h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
73 Simplified logic. dgisselq 2899d 04h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 2947d 05h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.		 dgisselq 2957d 04h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
50 Updates to fix some broken early branching code, both in idecode and pfcache. dgisselq 2966d 06h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.		 dgisselq 2977d 08h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
26 Some bug fixes, and the long jump early branching integration. dgisselq 2990d 08h /xulalx25soc/trunk/rtl/cpu/zipcpu.v
21 Files, not links, to replace what were once broken links in this project. dgisselq 3051d 17h /xulalx25soc/trunk/rtl/cpu/zipcpu.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.