URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [toplevel.v] - Rev 117

Rev	Log message	Author	Age	Path
117	Updates, to include new README and bench/cpp/Makefile that doesnt depend upon a static VERILATOR_ROOT location.	dgisselq	2753d 09h	/xulalx25soc/trunk/rtl/toplevel.v
113	Lots of updates, mostly focused on getting the XuLA board and CPU able to pass a comprehensive test suite. At this point, everything passes and logic usage is down even. Among the few changes includes the "break" bit in the uCC register, used to indicate a switch to supervisor mode occurred as a result of a user break, and the ability for the supervisor to clear the instruction cache.	dgisselq	2846d 10h	/xulalx25soc/trunk/rtl/toplevel.v
71	Needed to play with subtle timing to get this to build. Expect me to play with these two clock numbers more.	dgisselq	2884d 05h	/xulalx25soc/trunk/rtl/toplevel.v
48	Cleaned up the documentation a touch. It no longer reads like the bugs I used to debug are still being debugged ...	dgisselq	2962d 09h	/xulalx25soc/trunk/rtl/toplevel.v
18	Got the bitfile back up to speed at 80 MHz.	dgisselq	3040d 08h	/xulalx25soc/trunk/rtl/toplevel.v
9	Bug fixes, optimizations, etc. as part of building for an actual hardware implementation. Most notably, the speed was lowered from 80MHz down to 76 MHz.	dgisselq	3042d 07h	/xulalx25soc/trunk/rtl/toplevel.v
2	A very first, albeit incomplete, build.	dgisselq	3045d 04h	/xulalx25soc/trunk/rtl/toplevel.v