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[/] [xulalx25soc/] [trunk/] [rtl/] [wbpwmaudio.v] - Rev 113

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113 Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache.		 dgisselq 2846d 11h /xulalx25soc/trunk/rtl/wbpwmaudio.v
63 Simplified logic. dgisselq 2884d 06h /xulalx25soc/trunk/rtl/wbpwmaudio.v
56 Brings code in line with the OpenCores core: parameterizes the reload value,
and the number of bits in the timer.		 dgisselq 2892d 06h /xulalx25soc/trunk/rtl/wbpwmaudio.v
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.		 dgisselq 2962d 10h /xulalx25soc/trunk/rtl/wbpwmaudio.v
34 Bug fix: This sets as a positive voltage bias (not negative) the maximum
value of 0x07fff, where as the negative maximum value of 0x08000 properly
(now) reflects nearly ground--as one would desire. (Last time around I had
these backwards.)		 dgisselq 2974d 06h /xulalx25soc/trunk/rtl/wbpwmaudio.v
32 Just noticed that the timer was fixed on this. This change adjusts the
timer to support audio at a user selectable rate.		 dgisselq 2974d 08h /xulalx25soc/trunk/rtl/wbpwmaudio.v
9 Bug fixes, optimizations, etc. as part of building for an actual hardware
implementation. Most notably, the speed was lowered from 80MHz down to
76 MHz.		 dgisselq 3042d 07h /xulalx25soc/trunk/rtl/wbpwmaudio.v
8 Added an interface description to the comments at the top of the file. dgisselq 3044d 17h /xulalx25soc/trunk/rtl/wbpwmaudio.v
2 A very first, albeit incomplete, build. dgisselq 3045d 04h /xulalx25soc/trunk/rtl/wbpwmaudio.v

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