URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [xula.ucf] - Rev 118

Rev	Log message	Author	Age	Path
118	Lots of changes. The biggest are to the CPU: MPYxHI instructions are now verified to be working, ILLegal instructions stop at the right location, the STEP bit no longer self-clears, etc. Other changes cleaned up the internal documentation and removed parameters that should only have local scope from the global parameter list. The NEW_INSTRUCTION_SET was also removed from the CPU, since ... it's been new for too long to really be new anymore.	dgisselq	2730d 14h	/xulalx25soc/trunk/xula.ucf
117	Updates, to include new README and bench/cpp/Makefile that doesnt depend upon a static VERILATOR_ROOT location.	dgisselq	2755d 05h	/xulalx25soc/trunk/xula.ucf
113	Lots of updates, mostly focused on getting the XuLA board and CPU able to pass a comprehensive test suite. At this point, everything passes and logic usage is down even. Among the few changes includes the "break" bit in the uCC register, used to indicate a switch to supervisor mode occurred as a result of a user break, and the ability for the supervisor to clear the instruction cache.	dgisselq	2848d 07h	/xulalx25soc/trunk/xula.ucf
71	Needed to play with subtle timing to get this to build. Expect me to play with these two clock numbers more.	dgisselq	2886d 02h	/xulalx25soc/trunk/xula.ucf
6	Initial file load, likely to be buggy, but the initial load nonetheless.	dgisselq	3046d 23h	/xulalx25soc/trunk/xula.ucf