| Rev |
Log message |
Author |
Age |
Path |
| 39 |
An attempt at a bugfix. We'll see if this works any better downstream. |
dgisselq |
2987d 03h |
/ |
| 38 |
Updated to remove the build dependence upon ZipCPU. |
dgisselq |
2987d 07h |
/ |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
2988d 01h |
/ |
| 36 |
A linker script, appropriate to the XuLA25-LX25 SoC. |
dgisselq |
2988d 03h |
/ |
| 35 |
Updates the memory testing program to work successfully with the Gnu build
tools--particularly the GNU C-preprocessor from GCC and the GNU assembler from
Binutils. |
dgisselq |
2988d 03h |
/ |
| 34 |
Bug fix: This sets as a positive voltage bias (not negative) the maximum
value of 0x07fff, where as the negative maximum value of 0x08000 properly
(now) reflects nearly ground--as one would desire. (Last time around I had
these backwards.) |
dgisselq |
2991d 22h |
/ |
| 33 |
Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip. |
dgisselq |
2991d 23h |
/ |
| 32 |
Just noticed that the timer was fixed on this. This change adjusts the
timer to support audio at a user selectable rate. |
dgisselq |
2991d 23h |
/ |
| 31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
2992d 00h |
/ |
| 30 |
Bug fixes. In particular, this fixes a segmentation violation. |
dgisselq |
2992d 04h |
/ |
| 29 |
This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v) |
dgisselq |
2992d 20h |
/ |
| 28 |
Oops--two files needed by zipdbg weren't originally placed in the directory. |
dgisselq |
2993d 00h |
/ |
| 27 |
Bug fix: the last_state register now correctly reflects all 5-bits of the state
machine. (Useful when detecting lockups ...) |
dgisselq |
2993d 01h |
/ |
| 26 |
Some bug fixes, and the long jump early branching integration. |
dgisselq |
2993d 01h |
/ |
| 25 |
Fixing compile time warnings. |
dgisselq |
2993d 01h |
/ |
| 24 |
Added the #define necessary to enable (and clear) SCOPE interrupts. |
dgisselq |
2998d 23h |
/ |
| 23 |
This fixes a bug in the early branching system, and clarifies that early
branch instructions will not affect the flags. It's a basic bug fix update. |
dgisselq |
3001d 11h |
/ |
| 22 |
Added the mkdatev.pl file. (Oops!) |
dgisselq |
3004d 03h |
/ |
| 21 |
Files, not links, to replace what were once broken links in this project. |
dgisselq |
3054d 10h |
/ |
| 20 |
Documents, borrowed from their source projects, and reproduced here. These
describe the various components of the board. |
dgisselq |
3054d 10h |
/ |
