| Rev |
Log message |
Author |
Age |
Path |
| 55 |
Updated copyright notice. |
dgisselq |
2909d 23h |
/ |
| 54 |
Updated copyright notice. |
dgisselq |
2909d 23h |
/ |
| 53 |
Added a touch of error checking. |
dgisselq |
2950d 00h |
/ |
| 52 |
This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change. |
dgisselq |
2950d 00h |
/ |
| 51 |
Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags. |
dgisselq |
2959d 22h |
/ |
| 50 |
Updates to fix some broken early branching code, both in idecode and pfcache. |
dgisselq |
2969d 01h |
/ |
| 49 |
Added some documentation to make the read and write calls easier to understand. |
dgisselq |
2978d 01h |
/ |
| 48 |
Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ... |
dgisselq |
2980d 03h |
/ |
| 47 |
Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.) |
dgisselq |
2980d 03h |
/ |
| 46 |
This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles. |
dgisselq |
2980d 03h |
/ |
| 45 |
Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no
functional difference. |
dgisselq |
2983d 22h |
/ |
| 44 |
NELM parameter adjusted to reflect the maximum number of lines the compressed
scope can handle: 31, not 32. |
dgisselq |
2983d 23h |
/ |
| 43 |
Commentary changes only, no substance. |
dgisselq |
2983d 23h |
/ |
| 42 |
Minor changes. |
dgisselq |
2983d 23h |
/ |
| 41 |
Bug fix. This was preventing dumpsdram from accurately reading back what
had been written to the RAM earlier. |
dgisselq |
2983d 23h |
/ |
| 40 |
This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb. |
dgisselq |
2985d 09h |
/ |
| 39 |
An attempt at a bugfix. We'll see if this works any better downstream. |
dgisselq |
2987d 05h |
/ |
| 38 |
Updated to remove the build dependence upon ZipCPU. |
dgisselq |
2987d 08h |
/ |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
2988d 03h |
/ |
| 36 |
A linker script, appropriate to the XuLA25-LX25 SoC. |
dgisselq |
2988d 04h |
/ |
