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Rev Log message Author Age Path
74 Adds the SD-card capability, and connects the debug wires to/from the uartdev
in case it needs to be debugged.		 dgisselq 2897d 16h /
73 Simplified logic. dgisselq 2897d 16h /
72 Sets XULA25 as the default. dgisselq 2897d 16h /
71 Needed to play with subtle timing to get this to build. Expect me to play
with these two clock numbers more.		 dgisselq 2897d 16h /
70 Cosmetic (minor) update. dgisselq 2897d 17h /
69 Massive logic simplification. This is also the first (verified) working
version.		 dgisselq 2897d 17h /
68 Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb.
Fixed the multiply option parameter, so it sets a 3-clock multiply properly.
Adjusted the watchdog timer so that it now produces a timer that doesn't
reload--since this is pointless for a watchdog. Finally, connects a reset
line to the DMA, to make certain that resetting the CPU will also reset any
ongoing DMA operation.		 dgisselq 2897d 17h /
67 Simplifies logic, and guarantees that the minimum set value will always
produce an int. For example, if the count was X before, setting X-1 wouldn't
produce an interrupt since it had passed. Now it produces an interrupt, and
keeps the next interrupt valid.		 dgisselq 2897d 17h /
66 Simplified logic (barely). dgisselq 2897d 17h /
65 Makes the auto-reload feature a parameterized (generic) feature, so the same
code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog)
timers.		 dgisselq 2897d 17h /
64 First (verified) working version. dgisselq 2897d 17h /
63 Simplified logic. dgisselq 2897d 17h /
62 Removed the pipe logic from the non-pipelined version, and made the NOOP a
specific ALU instruction so that the PC is always properly updated.		 dgisselq 2897d 17h /
61 Fixed the timing control wires: busy and valid will never both be true. Busy
will be true (now) until valid is asserted, and busy will never not be
asserted until valid is true.		 dgisselq 2897d 17h /
60 LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a
MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively.		 dgisselq 2897d 17h /
59 Simplified logic. dgisselq 2897d 17h /
58 Bug fix: the UART can now be reconfigured post-boot without a BREAK condition. dgisselq 2897d 17h /
57 Fixed the TX/RX addresses so that they match the documentation: TX first, then
RX.		 dgisselq 2905d 17h /
56 Brings code in line with the OpenCores core: parameterizes the reload value,
and the number of bits in the timer.		 dgisselq 2905d 17h /
55 Updated copyright notice. dgisselq 2905d 17h /

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