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[/] [y80e/] - Rev 13

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Rev Log message Author Age Path
13 Updated instruction set table bsa 1661d 12h /y80e/
12 Added SVN property eol-style:native bsa 1661d 13h /y80e/
11 Added memory initialization files for testbench bsa 1661d 13h /y80e/
10 Added mnemonic list bsa 3986d 00h /y80e/
9 bsa 3986d 12h /y80e/
8 Added support for Zilog eZ80 instructions

Added support for all eZ80 instructions which works in non-ADL mode
(i.e. 16-bit address mode only).
bsa 3986d 12h /y80e/
7 bsa 3986d 13h /y80e/
6 Added support for Z180 instructions bsa 3986d 13h /y80e/
5 This version is compatible with Zilog Z80 CPU

Instructions RES/SET (ii+d),r is unsupported
Nonstandard NEG and others ED-prefixed are also unsupported
bsa 3986d 13h /y80e/
4 Added support for commonly used Z80 undocumented instructions

This instructions includes:
- operations with halfs of IX and IY registers
- undocumented shift instruction SLI (or SLL - Shift Left Logically)
Also added emulation of R register
bsa 3986d 13h /y80e/
3 Complete Y80 implementation.

This version of CPU is described in book 'Microprocessor Design Using Verilog
HDL' by Monte Dalryple from Systemyde. control.v file completed by me and
author of CPU permits me to publish this project.
bsa 3986d 13h /y80e/
2 Completed Y80 from Systemyde w/o anything else bsa 3986d 13h /y80e/
1 The project and the structure was created root 3987d 01h /y80e/

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