OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] - Rev 161

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
141 Fixes two bugs: one causing merged strings in the read only string section to
be referenced at the wrong address, and the second which caused the assembler
to fail at SYMBOL-OFFSET references.
dgisselq 2454d 09h /
140 Minor changes, but fixes build of zippy_tb.cpp. dgisselq 2456d 22h /
139 Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details.
dgisselq 2459d 19h /
138 This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed.
dgisselq 2459d 19h /
137 This should (again) fix the bug of trying to build optest.cpp. dgisselq 2473d 13h /
136 Oops --- missed a couple HOST_WIDE_INT values in a printf. This casts them
to (long), so that we can work on both PC's and ARMs.
dgisselq 2473d 13h /
135 Replaced all occurrences of INTVAL(...) on printf lines with (long)INTVAL(...).
This should fix the problems zip-gcc was having while running on the ARM.
dgisselq 2473d 13h /
134 Working updates, to keep this up to date with the RTL code. dgisselq 2474d 10h /
133 Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies.
dgisselq 2474d 10h /
132 Lots of minor bug fixes. dgisselq 2474d 10h /

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.