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Rev	Log message	Author	Age	Path
169	Added details of LM32 to the (pre) ORConf survey slide in trunk/doc.	dgisselq	2833d 03h	/
168	An updated version of the intensive CPU test. This one runs from C, and requires a UART port and a PIC, but can run quite successfully on multiple SoCs that have been built with the ZipCPU internal to them.	dgisselq	2846d 03h	/
167	Updated the spec to reflect changes in the CC register: the user break flag, and the ability to command a clearing of the instruction cache.	dgisselq	2846d 03h	/
166	Bugfix version. This fixes a problem whereby function addresses with offsets were not properly calculated, together with properly setting up pcrelative offsets when using the move function together with a label.	dgisselq	2846d 07h	/
165	Added a test to make certain that the arithmetic right shift was properly propagating the high order bit. (The test works under verilator, but didn't initially work in Xilinx -- thus a difference between the two.)	dgisselq	2846d 07h	/
164	Updated with inputs from Hellwig Geisse regarding the details of the ECO32 CPU.	dgisselq	2854d 09h	/
163	Trimmed OR1K instruction set down from 219 instructions, to the minimum number of 48. Thanks to Olof for helping identify the minimal set!	dgisselq	2862d 11h	/
162	Noted 64-bit integers are by extension, as are vector instructions.	dgisselq	2862d 11h	/
161	Initial version of the ORConf slides, showing only the initial CPU survey.	dgisselq	2862d 12h	/
160	Logic updates, and bug fix corrections to bring this in line with the current XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved, this update pushes those improvements to the mainline.)	dgisselq	2877d 23h	/

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