OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] - Rev 205

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
185 Now includes the proper flags for building with ELF executable file support. dgisselq 2080d 07h /
184 Adjusted the illegal instruction option documentation. dgisselq 2080d 07h /
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2080d 07h /
182 Bug fix for fast memories. This now works for memories with single cycle
latencies.
dgisselq 2080d 07h /
181 Adjusted the wishbone logic to include our wishbone simplification that if
CYC is ever low, STB must be low as well.
dgisselq 2080d 07h /
180 Cleaned up the stall logic--made it independent of whether or not we are
designed to be alternating or not.
dgisselq 2080d 07h /
179 Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary.
dgisselq 2080d 07h /
178 Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
LUTs.
dgisselq 2080d 07h /
177 Fixed the illegal address logic to be more precise. dgisselq 2080d 07h /
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
speed.
dgisselq 2080d 07h /

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.