OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] - Rev 54

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
54 This builds on the support for backslash character escapes in both single
and multicharacter expressions. Backslash character escapes are now
possible with quotations and backslashes, and the same code to interpret
the escapes is applied to both single and multicharacter sequences.
dgisselq 3146d 08h /
53 Updated the #include/#define directives to work properly for nested includes.
(They were supposed to work properly for nested includes before ... and didn't)
This fixes those bugs.
dgisselq 3146d 08h /
52 Added the capability to "see" character's encoded within a binary file,
by printing the character value(s) of each opcode (if they are printable)
on each line.
dgisselq 3146d 08h /
51 Added the capability to look at binary files and 'see' characters as they
are encoded in memory.
dgisselq 3146d 08h /
50 Dhrystone benchmark updates--added the copyright notice. (Oops!) dgisselq 3155d 23h /
49 Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works.
dgisselq 3155d 23h /
48 Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction.
dgisselq 3155d 23h /
47 Added some new graphics, includes the file for the Zip Bones system. dgisselq 3155d 23h /
46 A series of updates associated with getting Dhrystone to work. Includes
updates to getting multiple files to link/work together within the assembler,
as well as getting quoted quotations to work in the lexer, and better
include file support in the preprocessor.
dgisselq 3155d 23h /
45 Library routines for 32-bit multiply and divide, both signed and unsigned. dgisselq 3155d 23h /
44 ?? dgisselq 3155d 23h /
43 Minor edits to the C++ testbench. dgisselq 3155d 23h /
42 Oops -- forgot to add the stack. dgisselq 3155d 23h /
41 Assembly file for the Dhrystone benchmark added. dgisselq 3155d 23h /
40 Quick update, updates the assembly for the new version of the assembler. dgisselq 3155d 23h /
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.
dgisselq 3159d 02h /
38 A couple of quick updates:

- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.

Documentation changes coming shortly.
dgisselq 3159d 04h /
37 Fixed some minor spelling errors. dgisselq 3167d 19h /
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 3168d 08h /
35 I updated the system diagram to reflect the new version that has a direct
memory access controller, rather than the (useless) manual cache.
dgisselq 3184d 22h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.