URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] - Rev 64

Rev	Log message	Author	Age	Path
44	??	dgisselq	3139d 16h	/
43	Minor edits to the C++ testbench.	dgisselq	3139d 16h	/
42	Oops -- forgot to add the stack.	dgisselq	3139d 17h	/
41	Assembly file for the Dhrystone benchmark added.	dgisselq	3139d 17h	/
40	Quick update, updates the assembly for the new version of the assembler.	dgisselq	3139d 17h	/
39	Here's the documentation update to support the pipelined read/writes of the bus from the CPU, as well as the test file that proved they worked.	dgisselq	3142d 19h	/
38	A couple of quick updates: - The Zip CPU now supports pipelined memory access at one clock per instruction (assuming all the instructions are in the cache) - There is now a 'zipbones' module to build a Zip System without peripherals. Any peripherals would then need to be external to the CPU. - Some bug fixes. Documentation changes coming shortly.	dgisselq	3142d 21h	/
37	Fixed some minor spelling errors.	dgisselq	3151d 12h	/
36	Lots of changes to increase processing speed and remove pipeline stalls. Removed the useless flash cache, replacing it with a proper DMA controller. "make test" in the main directory now runs a test program in Verilator and reports on the results.	dgisselq	3152d 01h	/
35	I updated the system diagram to reflect the new version that has a direct memory access controller, rather than the (useless) manual cache.	dgisselq	3168d 15h	/