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44 ?? dgisselq 3125d 01h /
43 Minor edits to the C++ testbench. dgisselq 3125d 01h /
42 Oops -- forgot to add the stack. dgisselq 3125d 01h /
41 Assembly file for the Dhrystone benchmark added. dgisselq 3125d 01h /
40 Quick update, updates the assembly for the new version of the assembler. dgisselq 3125d 01h /
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.
dgisselq 3128d 03h /
38 A couple of quick updates:

- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.

Documentation changes coming shortly.
dgisselq 3128d 06h /
37 Fixed some minor spelling errors. dgisselq 3136d 20h /
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 3137d 09h /
35 I updated the system diagram to reflect the new version that has a direct
memory access controller, rather than the (useless) manual cache.
dgisselq 3154d 00h /

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