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Rev Log message Author Age Path
86 Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W).
dgisselq 3024d 18h /
85 Minor update/correction to operand B definition. dgisselq 3024d 18h /
84 Minor updates. dgisselq 3024d 18h /
83 Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)

Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)

Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true.
dgisselq 3024d 18h /
82 Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line.
dgisselq 3024d 18h /
81 Trying to clean up ISE generated warnings. dgisselq 3024d 18h /
80 Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining.
dgisselq 3024d 18h /
79 Adjusted the opcodes for NOOP, BREAK, and LOCK. dgisselq 3028d 22h /
78 Found/corrected annoying bug in floating point documentation of the opcode
table.
dgisselq 3028d 22h /
77 First check-in: the test bench for the divide instruction. dgisselq 3029d 21h /
76 The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions.
dgisselq 3029d 21h /
75 Modified for VLIW instructions. dgisselq 3029d 21h /
74 Added a bunch of debugging code to the Dhrystone benchmark assembly file, as
well as two new testing assembly files.
dgisselq 3029d 21h /
73 Documentations updates. dgisselq 3029d 21h /
72 Some updated graphics, now containing images of the CPU that include the
divide and (currently non-existant) floating point unit.
dgisselq 3029d 21h /
71 This contains a bunch of bug fixes. (A lot ...) For example, the pipeline
stall code has also seriously changed, to fixed the pipeline memory load/op
stage conflict, while maintaining no-stall operation for operands that don't
need an offset. This had a cascading effect, however, so that the multiply
could no longer complete in a single cycle. Therefore, the timing on the
multiplies was slowed down to two cycles from a single cycle. (It's the
only two-cycle ALU operation ...) The illegal instruction code has also been
fixed, so that illegal instructions no longer stalls the prefetch bus.
dgisselq 3029d 21h /
70 Updated the assembler support files, zopcodes in particular, to handle
the disassembly of the new very long instruction word codes.
dgisselq 3029d 21h /
69 This implements the "new Instruction Set" architecture for the Zip CPU. It's
a massive change set, that touches just about everything but probably not
enough of everything. Please see the spec.pdf for a description of this
new architecture.
dgisselq 3036d 02h /
68 Updated specification, includes well illustrated pipeline discussion. dgisselq 3071d 02h /
67 Includes timing diagrams in support of a very descriptive specification section. dgisselq 3071d 02h /

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