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Rev Log message Author Age Path
201 RTL files for the 8-bit capable ZipCPU. dgisselq 2626d 14h /.
200 Lots of GCC bugs fixed, some new features added, longs should work now. The
build scripts have also been updated and simplified.		 dgisselq 2725d 21h /.
199 Massive specification rewrite, brings it up to date with the current ZipCPU
state. This does not reflect any major change to the CPU.		 dgisselq 2751d 10h /.
198 Added a copyright notice. dgisselq 2752d 14h /.
197 Added a new multiply testbench. Other changes were necessary to follow. dgisselq 2752d 14h /.
196 Updated internal documentation. dgisselq 2752d 14h /.
195 Adds a new mode that can handle a delayed stall signal. dgisselq 2752d 14h /.
194 Cleaned up some parameters, trying to create more consistency. dgisselq 2752d 14h /.
193 These changes make it so the ALU multiplies pass a test-bench. dgisselq 2752d 14h /.
192 Fixed a bug with constant alignment in the assembler. dgisselq 2752d 14h /.
191 Updated toolchain, more information on the example debugger. dgisselq 2767d 17h /.
190 Added the copyright statement back in. dgisselq 2769d 09h /.
189 Final, as delivered, ORCONF slides. dgisselq 2769d 09h /.
188 Adjusted the opcodes to match the binutils port: added RTN instructions, and
allowed BREAK instructions to include an immediate--to be interpreted by the
debugger.		 dgisselq 2801d 11h /.
187 Updated to match changed register definitions within the core. dgisselq 2801d 12h /.
186 Now allows profile dumping for ELF executables. dgisselq 2801d 12h /.
185 Now includes the proper flags for building with ELF executable file support. dgisselq 2801d 12h /.
184 Adjusted the illegal instruction option documentation. dgisselq 2801d 12h /.
183 Cleaned up the system so that !CYC implies !STB as well. dgisselq 2801d 12h /.
182 Bug fix for fast memories. This now works for memories with single cycle
latencies.		 dgisselq 2801d 12h /.

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