URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] - Rev 102

Rev	Log message	Author	Age	Path
82	Found and (I hope) fixed a nasty bug that would send the prefetch into an endless loop whenever you jumped to an instruction at the last location in an unloaded cache line.	dgisselq	3059d 16h	/zipcpu
81	Trying to clean up ISE generated warnings.	dgisselq	3059d 16h	/zipcpu
80	Bug fix: declared the (combined) multiply to be signed again. Also changed the name of the generate'd for block, to keep ISE from complaining.	dgisselq	3059d 16h	/zipcpu
79	Adjusted the opcodes for NOOP, BREAK, and LOCK.	dgisselq	3063d 20h	/zipcpu
78	Found/corrected annoying bug in floating point documentation of the opcode table.	dgisselq	3063d 20h	/zipcpu
77	First check-in: the test bench for the divide instruction.	dgisselq	3064d 19h	/zipcpu
76	The biggest change here was to zippy_tb, to make it more similar to the debugger and to make it work with VLIW-type instructions.	dgisselq	3064d 19h	/zipcpu
75	Modified for VLIW instructions.	dgisselq	3064d 19h	/zipcpu
74	Added a bunch of debugging code to the Dhrystone benchmark assembly file, as well as two new testing assembly files.	dgisselq	3064d 19h	/zipcpu
73	Documentations updates.	dgisselq	3064d 19h	/zipcpu