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Rev Log message Author Age Path
95 Fixed a bug whereby a mistaken code for CLR was masking a valid LDI of a large
integer value.		 dgisselq 2985d 16h /zipcpu/
94 These changes make it possible to build binutils-2.25/ here in this
directory. "make binutils" should be all that is necessary to build the
entire binutils package for the Zip CPU.

The default configure script, run from gas-script.sh below, will build and
install these utilities in an install/ subdirectory made below sw/.		 dgisselq 3010d 13h /zipcpu/
93 A BINUTILS BACKEND IS NOW AVAILABLE!!!! dgisselq 3018d 11h /zipcpu/
92 Adjustments made to match the simplified early branching. dgisselq 3018d 11h /zipcpu/
91 Minor updates. dgisselq 3018d 11h /zipcpu/
90 Removed MOV x(PC),PC from the list of possible early branching instructions.
ADD X,PC and LDI X,PC are now the only recognized early branching instructions.
This was done to spare logic, although I don't think I spared more than a
LUT or two.		 dgisselq 3018d 11h /zipcpu/
89 Minor changes, to include making default branching an ADD.[condition] X,PC
instruction, rather than allowing both MOV X(PC),PC and ADD X,PC instructions.

Further zopcodes.cpp contains several bug fixes.		 dgisselq 3018d 11h /zipcpu/
88 Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ...		 dgisselq 3042d 11h /zipcpu/
87 Adjusted the operator input line to reflect actual logic inputs, rather
than the registered inputs which may have been out of date. (Indeed, they
were out of date for the bug I was chasing and fixed ...)		 dgisselq 3044d 09h /zipcpu/
86 Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W).		 dgisselq 3044d 09h /zipcpu/

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