OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] - Rev 137

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
137 This should (again) fix the bug of trying to build optest.cpp. dgisselq 3004d 19h /zipcpu/
136 Oops --- missed a couple HOST_WIDE_INT values in a printf. This casts them
to (long), so that we can work on both PC's and ARMs.
dgisselq 3004d 19h /zipcpu/
135 Replaced all occurrences of INTVAL(...) on printf lines with (long)INTVAL(...).
This should fix the problems zip-gcc was having while running on the ARM.
dgisselq 3004d 19h /zipcpu/
134 Working updates, to keep this up to date with the RTL code. dgisselq 3005d 16h /zipcpu/
133 Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies.
dgisselq 3005d 16h /zipcpu/
132 Lots of minor bug fixes. dgisselq 3005d 16h /zipcpu/
131 Fixed a variable use before declaration error. dgisselq 3005d 16h /zipcpu/
130 Simplified the lock logic, and removed it when pipelining was not defined. This
also means the file is now dependent upon cpudefs.v. In another change, brev
was modified so as not to update the flags. This makes it useable with GCC
as a potential move or load immediate instruction.
dgisselq 3005d 16h /zipcpu/
129 Bug fix. Fixes some ugly race conditions that would cause code from the wrong
address to be executed.
dgisselq 3005d 16h /zipcpu/
128 Cleaned up some comments. dgisselq 3005d 16h /zipcpu/
127 Lots of changes and bugfixes. The disassembler produces more readable output.
The assembler and linker will no longer automatically use LDIHI--in preparation
for switching to LONG_MPY. LDIHI/LDILO pairs have been changed to BREV/LDILO
pairs. Within the compiler, conditional moves have been rebuilt. They're not
perfect yet, but they are better. Lots of peephole optimizations, etc.
dgisselq 3005d 16h /zipcpu/
126 Lots of changes preparing the assembly for an instruction set change. While
implemented, they are still commented out via #ifdef LONG_MPY. By defining
LONG_MPY, this new change set will take place.
dgisselq 3005d 16h /zipcpu/
125 This patch contains minor updates. Two are important to mention: 1) It turns
the compare optimizations back on within the zip.md file, and 2) it fixes an
internal compiler fault that was causing the compiler to such up all of my
memory in an infinite recursion.
dgisselq 3014d 00h /zipcpu/
124 Lots of changes, lots of bugfixes--both to the compiler as well as to the
assembler. (Ex: the assembler will now properly execute a LDI _sym+5,R0).
Many compiler optimizations have been turned off, however. They will probably
be turned back on in the near future--once I get this version proven without
them.
dgisselq 3015d 14h /zipcpu/
123 This test now catches and tests some of the pipeline bugs I've been chasing. dgisselq 3015d 14h /zipcpu/
122 This represents a major rewrite of the machine definition file, gcc/config/zip/
zip.md. In particular, the architecture has been changed from a "cc0"
architecture to one with a specific CC_REG and CCmode. Instructions in the
machine definition file must now explicitly set this register with their
results. The result is better condition code handling, better usage of the
conditional execution modes of certain instructions, and even some decent
optimizations.
dgisselq 3020d 18h /zipcpu/
121 Fixed the bug whereby BGE instructions dissassembled as BGT instructions and
vice versa. Loads and stores of absolute addresses now show those addresses
in ($<>). The assembler also accepts integer offsets to symbols, although
it isn't clear that it does the "right" thing with them yet.
dgisselq 3020d 18h /zipcpu/
120 Should've regression tested that last build. This one fixes what that last
fix broke: Registers with offsets (i.e. operand-B) now work (again).
dgisselq 3024d 14h /zipcpu/
119 Fixed some limits bugs. Now LDI.Z 1 produces LDIHI.Z 0, LDOLO.Z 1 as desired
instead of the erroneous BREV.Z 0. Likewise, loading 0x80000000 no longer
produces a clear instruction, but actually loads the value of interest.
dgisselq 3024d 14h /zipcpu/
118 Fixes two bugs: 1) in the early branching code within the instruction decoder.
This prevented the early branching from working when built with Xilinx's tools,
while the code worked with Verilator. 2) The CPU was not working with the
traditional cache and early branching disabled. These two bugs masked each
other. The replacement code is simpler.
dgisselq 3024d 17h /zipcpu/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.