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126 Lots of changes preparing the assembly for an instruction set change. While
implemented, they are still commented out via #ifdef LONG_MPY. By defining
LONG_MPY, this new change set will take place.		 dgisselq 2934d 22h /zipcpu/
125 This patch contains minor updates. Two are important to mention: 1) It turns
the compare optimizations back on within the zip.md file, and 2) it fixes an
internal compiler fault that was causing the compiler to such up all of my
memory in an infinite recursion.		 dgisselq 2943d 06h /zipcpu/
124 Lots of changes, lots of bugfixes--both to the compiler as well as to the
assembler. (Ex: the assembler will now properly execute a LDI _sym+5,R0).
Many compiler optimizations have been turned off, however. They will probably
be turned back on in the near future--once I get this version proven without
them.		 dgisselq 2944d 20h /zipcpu/
123 This test now catches and tests some of the pipeline bugs I've been chasing. dgisselq 2944d 20h /zipcpu/
122 This represents a major rewrite of the machine definition file, gcc/config/zip/
zip.md. In particular, the architecture has been changed from a "cc0"
architecture to one with a specific CC_REG and CCmode. Instructions in the
machine definition file must now explicitly set this register with their
results. The result is better condition code handling, better usage of the
conditional execution modes of certain instructions, and even some decent
optimizations.		 dgisselq 2950d 00h /zipcpu/
121 Fixed the bug whereby BGE instructions dissassembled as BGT instructions and
vice versa. Loads and stores of absolute addresses now show those addresses
in ($<>). The assembler also accepts integer offsets to symbols, although
it isn't clear that it does the "right" thing with them yet.		 dgisselq 2950d 00h /zipcpu/
120 Should've regression tested that last build. This one fixes what that last
fix broke: Registers with offsets (i.e. operand-B) now work (again).		 dgisselq 2953d 20h /zipcpu/
119 Fixed some limits bugs. Now LDI.Z 1 produces LDIHI.Z 0, LDOLO.Z 1 as desired
instead of the erroneous BREV.Z 0. Likewise, loading 0x80000000 no longer
produces a clear instruction, but actually loads the value of interest.		 dgisselq 2953d 20h /zipcpu/
118 Fixes two bugs: 1) in the early branching code within the instruction decoder.
This prevented the early branching from working when built with Xilinx's tools,
while the code worked with Verilator. 2) The CPU was not working with the
traditional cache and early branching disabled. These two bugs masked each
other. The replacement code is simpler.		 dgisselq 2953d 23h /zipcpu/
117 Bug fixes: This adds the zip_ucc() instruction as a builtin, fixes the zip_cc()
builtin (both are now unspec_volatile) together with fixing the *_context(int*)
builtins so that they use five registers, never four. Further, this fixes the
negative stack space offset bug. Many of the GCC files now have Zip debugging
hooks within them as well, to simplify further debugging of the compiler.		 dgisselq 2954d 06h /zipcpu/

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