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[/] [zipcpu/] - Rev 15

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15 Updated the core CPUOPS module to make certain that the carry was properly
set on right shifts. (Carry is then the last bit shifted out to the right,
and has no relation to the high order bits of the word.) Also fixed a bug
in the busdelay.v file that prevented our Quad SPI flash controller from
working. (This bug fix has not yet been tested ...) Our test.S program, the
closest thing we have to a regression test and found in the sw/zasm directory,
still successfully passes in Verilator.
dgisselq 2670d 11h /zipcpu/
14 Removing zasm.cpp--the old assembler that never worked well. dgisselq 2670d 12h /zipcpu/
13 Finally! The beginnings of the new assembler. It's not really polished yet,
and it is quite clunky, but it works!! (Lots of bugs and features left to
fix/implement: #include, #define macro(), #line tracking through the
preprocessor, a means of finding include files (and the preprocessor!) and
more. But, as a beginning, the basics are functinoal.
dgisselq 2670d 12h /zipcpu/
12 Bunch of changes while trying to get a hello world program:
1. Right shifts by 32 or more now result in zero, or all of the top bit in the
case of ASRs.
2. zdump now properly includes addresses with dumped lines.
3. zparser now properly handles immediate values via the .DAT instruction.
dgisselq 2685d 03h /zipcpu/
11 This version works on an FPGA!!!

(Or at least the wdt.S program passes ...)
dgisselq 2685d 11h /zipcpu/
10 Here's the watchdog timer code, as well as some pictures of the register
set.
dgisselq 2686d 01h /zipcpu/
9 This checkin is the result of a watchdog timer test, and everything it took
to get the watchdog timer working. The timer function was simplified,
although it now uses a touch more resources--being able to count down 31
bits instead of 30. The parser was modified, since it couldn't handle
storing to register plus offsets like it was supposed to be able to. The
testbench, zippy_tb, was modified to accept an assembled machine code file
such as I might place on a board to test it.

Lots of work to get it working.

Looking at the files below, it looks like I'll need a second check in to check
in the watchdog timer test itself.
dgisselq 2686d 01h /zipcpu/
8 Fixed the rotate left instruction to work in the zasm parser, and to be
properly referenced in the simulator. The instruction set documentation was
also adjusted to reflect what the CPU actually does.
dgisselq 2686d 07h /zipcpu/
7 Here's the iset.html file that was at one time in the gfx directory, but
which could not be moved due to a bad gateway error ... (Grrr).
dgisselq 2686d 08h /zipcpu/
6 Trying to move iset.html from gfx directory. dgisselq 2686d 08h /zipcpu/
5 Updated colors in the graphics. dgisselq 2686d 08h /zipcpu/
4 dgisselq 2686d 08h /zipcpu/
3 Rebuilt the pipefetch (instruction fetch/cache module) so that it will
let go of the bus if the memory unit wants it to execute an instruction.
Pipefetch will then grab the bus back whtn the memory unit is done, so things
otherwise continue as they were before.

Other tweaks were made to try to reduce code complexity.
dgisselq 2686d 08h /zipcpu/
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2687d 01h /zipcpu/
1 The project and the structure was created root 2687d 07h /zipcpu/

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