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[/] [zipcpu/] - Rev 155

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Rev Log message Author Age Path
135 Replaced all occurrences of INTVAL(...) on printf lines with (long)INTVAL(...).
This should fix the problems zip-gcc was having while running on the ARM.		 dgisselq 2933d 14h /zipcpu
134 Working updates, to keep this up to date with the RTL code. dgisselq 2934d 11h /zipcpu
133 Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies.		 dgisselq 2934d 11h /zipcpu
132 Lots of minor bug fixes. dgisselq 2934d 11h /zipcpu
131 Fixed a variable use before declaration error. dgisselq 2934d 11h /zipcpu
130 Simplified the lock logic, and removed it when pipelining was not defined. This
also means the file is now dependent upon cpudefs.v. In another change, brev
was modified so as not to update the flags. This makes it useable with GCC
as a potential move or load immediate instruction.		 dgisselq 2934d 11h /zipcpu
129 Bug fix. Fixes some ugly race conditions that would cause code from the wrong
address to be executed.		 dgisselq 2934d 11h /zipcpu
128 Cleaned up some comments. dgisselq 2934d 11h /zipcpu
127 Lots of changes and bugfixes. The disassembler produces more readable output.
The assembler and linker will no longer automatically use LDIHI--in preparation
for switching to LONG_MPY. LDIHI/LDILO pairs have been changed to BREV/LDILO
pairs. Within the compiler, conditional moves have been rebuilt. They're not
perfect yet, but they are better. Lots of peephole optimizations, etc.		 dgisselq 2934d 11h /zipcpu
126 Lots of changes preparing the assembly for an instruction set change. While
implemented, they are still commented out via #ifdef LONG_MPY. By defining
LONG_MPY, this new change set will take place.		 dgisselq 2934d 11h /zipcpu

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