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[/] [zipcpu/] - Rev 159

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139 Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details.		 dgisselq 2933d 07h /zipcpu
138 This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed.		 dgisselq 2933d 07h /zipcpu
137 This should (again) fix the bug of trying to build optest.cpp. dgisselq 2947d 00h /zipcpu
136 Oops --- missed a couple HOST_WIDE_INT values in a printf. This casts them
to (long), so that we can work on both PC's and ARMs.		 dgisselq 2947d 01h /zipcpu
135 Replaced all occurrences of INTVAL(...) on printf lines with (long)INTVAL(...).
This should fix the problems zip-gcc was having while running on the ARM.		 dgisselq 2947d 01h /zipcpu
134 Working updates, to keep this up to date with the RTL code. dgisselq 2947d 21h /zipcpu
133 Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies.		 dgisselq 2947d 22h /zipcpu
132 Lots of minor bug fixes. dgisselq 2947d 22h /zipcpu
131 Fixed a variable use before declaration error. dgisselq 2947d 22h /zipcpu
130 Simplified the lock logic, and removed it when pipelining was not defined. This
also means the file is now dependent upon cpudefs.v. In another change, brev
was modified so as not to update the flags. This makes it useable with GCC
as a potential move or load immediate instruction.		 dgisselq 2947d 22h /zipcpu

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