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[/] [zipcpu/] - Rev 162

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Rev Log message Author Age Path
142 Bug fix--fixes some problems with conditional execution, as well as removing
an unnecessary peephole optimization.
dgisselq 3068d 02h /zipcpu/
141 Fixes two bugs: one causing merged strings in the read only string section to
be referenced at the wrong address, and the second which caused the assembler
to fail at SYMBOL-OFFSET references.
dgisselq 3068d 03h /zipcpu/
140 Minor changes, but fixes build of zippy_tb.cpp. dgisselq 3070d 15h /zipcpu/
139 Changes necessary to document the changed instruction set: LDIHI became MPY,
and MPYU and MPYS became MPYUHI and MPYSHI respectively. See the specification
for more details.
dgisselq 3073d 12h /zipcpu/
138 This updates the CPU multiply instruction into a set of three instructions.
MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
returns the upper 32-bits assuming the result was signed.
dgisselq 3073d 12h /zipcpu/
137 This should (again) fix the bug of trying to build optest.cpp. dgisselq 3087d 06h /zipcpu/
136 Oops --- missed a couple HOST_WIDE_INT values in a printf. This casts them
to (long), so that we can work on both PC's and ARMs.
dgisselq 3087d 06h /zipcpu/
135 Replaced all occurrences of INTVAL(...) on printf lines with (long)INTVAL(...).
This should fix the problems zip-gcc was having while running on the ARM.
dgisselq 3087d 06h /zipcpu/
134 Working updates, to keep this up to date with the RTL code. dgisselq 3088d 03h /zipcpu/
133 Changes preceding an instruction set update, which will change the multiply
operation from a 16x16 bit multiply to three types of 32x32-bit multiplies.
dgisselq 3088d 03h /zipcpu/

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