OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] - Rev 176

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
speed.
dgisselq 2719d 19h /zipcpu/
175 Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register.
dgisselq 2719d 19h /zipcpu/
174 Simplified the divide to improve timing performance. dgisselq 2719d 19h /zipcpu/
173 Adjusted the pdfinfo field, to accommodate Google's bot. dgisselq 2719d 19h /zipcpu/
172 Added a test to see if the compiler properly handles a large number of
arguments. Further, the sibcall enabled compiler now correcly makes a
sibcall from the end of txreg().
dgisselq 2719d 19h /zipcpu/
171 This fixes the problem whereby the ZipCPU didn't properly access more than
5 word-sized function parameters.
dgisselq 2722d 00h /zipcpu/
170 Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line.
dgisselq 2731d 18h /zipcpu/
169 Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. dgisselq 2767d 19h /zipcpu/
168 An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them.
dgisselq 2780d 19h /zipcpu/
167 Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache.
dgisselq 2780d 19h /zipcpu/
166 Bugfix version. This fixes a problem whereby function addresses with offsets
were not properly calculated, together with properly setting up pcrelative
offsets when using the move function together with a label.
dgisselq 2780d 23h /zipcpu/
165 Added a test to make certain that the arithmetic right shift was properly
propagating the high order bit. (The test works under verilator, but didn't
initially work in Xilinx -- thus a difference between the two.)
dgisselq 2780d 23h /zipcpu/
164 Updated with inputs from Hellwig Geisse regarding the details of the ECO32
CPU.
dgisselq 2789d 00h /zipcpu/
163 Trimmed OR1K instruction set down from 219 instructions, to the minimum number
of 48. Thanks to Olof for helping identify the minimal set!
dgisselq 2797d 02h /zipcpu/
162 Noted 64-bit integers are by extension, as are vector instructions. dgisselq 2797d 03h /zipcpu/
161 Initial version of the ORConf slides, showing only the initial CPU survey. dgisselq 2797d 03h /zipcpu/
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)
dgisselq 2812d 14h /zipcpu/
159 Now supports building a simulator that can load ELF files, such as GCC and/or
binutils will produce.
dgisselq 2812d 15h /zipcpu/
158 Now automatically builds the toolchain by default. dgisselq 2812d 15h /zipcpu/
157 Added the divide unit to the list of ZipCPU dependencies. dgisselq 2812d 15h /zipcpu/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.