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179 Lots of changes, most (all?) of them to the non-pipelined core. The resulting
core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains
the pipelined logic when necessary.
dgisselq 2114d 09h /zipcpu/
178 Rewrote the parameter controlled logic to be just that: perameter controller,
rather than depending upon generics. The result reduces our area by a couple
LUTs.
dgisselq 2114d 09h /zipcpu/
177 Fixed the illegal address logic to be more precise. dgisselq 2114d 09h /zipcpu/
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
speed.
dgisselq 2114d 09h /zipcpu/
175 Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register.
dgisselq 2114d 09h /zipcpu/
174 Simplified the divide to improve timing performance. dgisselq 2114d 09h /zipcpu/
173 Adjusted the pdfinfo field, to accommodate Google's bot. dgisselq 2114d 09h /zipcpu/
172 Added a test to see if the compiler properly handles a large number of
arguments. Further, the sibcall enabled compiler now correcly makes a
sibcall from the end of txreg().
dgisselq 2114d 09h /zipcpu/
171 This fixes the problem whereby the ZipCPU didn't properly access more than
5 word-sized function parameters.
dgisselq 2116d 14h /zipcpu/
170 Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line.
dgisselq 2126d 08h /zipcpu/
169 Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. dgisselq 2162d 09h /zipcpu/
168 An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them.
dgisselq 2175d 09h /zipcpu/
167 Updated the spec to reflect changes in the CC register: the user break
flag, and the ability to command a clearing of the instruction cache.
dgisselq 2175d 09h /zipcpu/
166 Bugfix version. This fixes a problem whereby function addresses with offsets
were not properly calculated, together with properly setting up pcrelative
offsets when using the move function together with a label.
dgisselq 2175d 13h /zipcpu/
165 Added a test to make certain that the arithmetic right shift was properly
propagating the high order bit. (The test works under verilator, but didn't
initially work in Xilinx -- thus a difference between the two.)
dgisselq 2175d 13h /zipcpu/
164 Updated with inputs from Hellwig Geisse regarding the details of the ECO32
CPU.
dgisselq 2183d 14h /zipcpu/
163 Trimmed OR1K instruction set down from 219 instructions, to the minimum number
of 48. Thanks to Olof for helping identify the minimal set!
dgisselq 2191d 16h /zipcpu/
162 Noted 64-bit integers are by extension, as are vector instructions. dgisselq 2191d 17h /zipcpu/
161 Initial version of the ORConf slides, showing only the initial CPU survey. dgisselq 2191d 17h /zipcpu/
160 Logic updates, and bug fix corrections to bring this in line with the current
XuLA2-LX25 SoC version. (i.e., the XuLA version was debugged and improved,
this update pushes those improvements to the mainline.)
dgisselq 2207d 05h /zipcpu/

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