Subversion Repositories zipcpu

[/] [zipcpu/] - Rev 197


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
177 Fixed the illegal address logic to be more precise. dgisselq 2079d 22h /zipcpu/
176 Switched from distributed to block RAM, and adjusted the logic to help
timing closure. The resulting core will build in designs up to 200MHz in
dgisselq 2079d 22h /zipcpu/
175 Fixed the carry bit for logical shifts: it is the last bit shifted out of the
register. 0x80000000>>32 yields a 0 with carry set. Anything logically
shifted by a number greater than thirty two clears carry and register.
dgisselq 2079d 22h /zipcpu/
174 Simplified the divide to improve timing performance. dgisselq 2079d 22h /zipcpu/
173 Adjusted the pdfinfo field, to accommodate Google's bot. dgisselq 2079d 22h /zipcpu/
172 Added a test to see if the compiler properly handles a large number of
arguments. Further, the sibcall enabled compiler now correcly makes a
sibcall from the end of txreg().
dgisselq 2079d 22h /zipcpu/
171 This fixes the problem whereby the ZipCPU didn't properly access more than
5 word-sized function parameters.
dgisselq 2082d 04h /zipcpu/
170 Minor updates to the orconf.pdf pre-conference slide. (Added the 'to be
revealed' line.
dgisselq 2091d 22h /zipcpu/
169 Added details of LM32 to the (pre) ORConf survey slide in trunk/doc. dgisselq 2127d 22h /zipcpu/
168 An updated version of the intensive CPU test. This one runs from C, and
requires a UART port and a PIC, but can run quite successfully on multiple
SoCs that have been built with the ZipCPU internal to them.
dgisselq 2140d 22h /zipcpu/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.