URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] - Rev 205

Rev	Log message	Author	Age	Path
185	Now includes the proper flags for building with ELF executable file support.	dgisselq	2779d 10h	/zipcpu/
184	Adjusted the illegal instruction option documentation.	dgisselq	2779d 10h	/zipcpu/
183	Cleaned up the system so that !CYC implies !STB as well.	dgisselq	2779d 10h	/zipcpu/
182	Bug fix for fast memories. This now works for memories with single cycle latencies.	dgisselq	2779d 11h	/zipcpu/
181	Adjusted the wishbone logic to include our wishbone simplification that if CYC is ever low, STB must be low as well.	dgisselq	2779d 11h	/zipcpu/
180	Cleaned up the stall logic--made it independent of whether or not we are designed to be alternating or not.	dgisselq	2779d 11h	/zipcpu/
179	Lots of changes, most (all?) of them to the non-pipelined core. The resulting core is now about 100-120 LUTs smaller when not-pipelined, and yet maintains the pipelined logic when necessary.	dgisselq	2779d 11h	/zipcpu/
178	Rewrote the parameter controlled logic to be just that: perameter controller, rather than depending upon generics. The result reduces our area by a couple LUTs.	dgisselq	2779d 11h	/zipcpu/
177	Fixed the illegal address logic to be more precise.	dgisselq	2779d 11h	/zipcpu/
176	Switched from distributed to block RAM, and adjusted the logic to help timing closure. The resulting core will build in designs up to 200MHz in speed.	dgisselq	2779d 11h	/zipcpu/