URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] - Rev 28

Rev	Log message	Author	Age	Path
8	Fixed the rotate left instruction to work in the zasm parser, and to be properly referenced in the simulator. The instruction set documentation was also adjusted to reflect what the CPU actually does.	dgisselq	3210d 08h	/zipcpu/
7	Here's the iset.html file that was at one time in the gfx directory, but which could not be moved due to a bad gateway error ... (Grrr).	dgisselq	3210d 09h	/zipcpu/
6	Trying to move iset.html from gfx directory.	dgisselq	3210d 09h	/zipcpu/
5	Updated colors in the graphics.	dgisselq	3210d 10h	/zipcpu/
4		dgisselq	3210d 10h	/zipcpu/
3	Rebuilt the pipefetch (instruction fetch/cache module) so that it will let go of the bus if the memory unit wants it to execute an instruction. Pipefetch will then grab the bus back whtn the memory unit is done, so things otherwise continue as they were before. Other tweaks were made to try to reduce code complexity.	dgisselq	3210d 10h	/zipcpu/
2	An initial load. No promises of what works or not, but this is where the project is at.	dgisselq	3211d 03h	/zipcpu/
1	The project and the structure was created	root	3211d 08h	/zipcpu/