OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] - Rev 61

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
61 Simplified the bus delay logic. Depends upon the stall line being irrelevant
outside of a bus cycle.
dgisselq 2659d 23h /zipcpu/
60 Fixed assembler processing of jump instructions, so that the new fast
return instruction can be used. The test file was modified to test
pipelined value passing within the CPU. That's where the value gets
(re)used before being stored back in the register file. As of this release,
all tests work.
dgisselq 2659d 23h /zipcpu/
59 Adjusted these library routines to use the new stack frame and calling
conventions.
dgisselq 2659d 23h /zipcpu/
58 Added a rudimentary profiling support to the simulator. dgisselq 2659d 23h /zipcpu/
57 Some bug fixes to the dhrystone benchmark, and some compile time defines for
the test bench processor. Of the most important note is the fix to detect
lockups on the debug/wishbone bus--that has been a real help in getting the
ZipCPU installed and the debugger working on the various boards I'm working
with. (i.e., it's helped me find and figure out why/when things haven't worked)
Of other note is the new 'G' key in the testbench code, to cause the test
bench to run without user interaction until the next keystroke. This is
very valuable in long programs, as it makes getting to/from breakpoints
easier (i.e. you don't have to wait as long, hit 'G', breathe, hit 'space'
and you're there).
dgisselq 2670d 01h /zipcpu/
56 Here's a bit of work in progress for getting the Zip CPU working on a XuLA2
board. Many changes include: the existence of a cpudefs.v file to control
what "options" are included in the ZipCPU build. This allows build control
to be separated from the project directory (one build for a XuLA2 board,
another for a Basys-3 development board). Other changes have made things
perhaps harder to read, but they get rid of warnings from XST.

A big change was the addition of the (* ram_style="distributed" *) comment
for the register set. This was necessary to keep XST from inferring a block
RAM and breaking the logic that was supposed to take place between a register
read and when it was used.
dgisselq 2670d 01h /zipcpu/
55 A test was added to double check whether carry following right shifts worked.
This was a necessary part of getting two cycle linear feedback shift register
operations working for a memory test on a XuLA2 board. With this, I can now
verify that such feedback registers work for pseudorandom number purposes.
dgisselq 2670d 01h /zipcpu/
54 This builds on the support for backslash character escapes in both single
and multicharacter expressions. Backslash character escapes are now
possible with quotations and backslashes, and the same code to interpret
the escapes is applied to both single and multicharacter sequences.
dgisselq 2670d 01h /zipcpu/
53 Updated the #include/#define directives to work properly for nested includes.
(They were supposed to work properly for nested includes before ... and didn't)
This fixes those bugs.
dgisselq 2670d 01h /zipcpu/
52 Added the capability to "see" character's encoded within a binary file,
by printing the character value(s) of each opcode (if they are printable)
on each line.
dgisselq 2670d 01h /zipcpu/
51 Added the capability to look at binary files and 'see' characters as they
are encoded in memory.
dgisselq 2670d 01h /zipcpu/
50 Dhrystone benchmark updates--added the copyright notice. (Oops!) dgisselq 2679d 17h /zipcpu/
49 Final set of changes finishing the Dhrystone package. Dhrystone, as
implemented by hand in assembly, now works.
dgisselq 2679d 17h /zipcpu/
48 Files added/updated to get Dhrystone benchmark to work. Several fixes
to the CPU in the process, 'cause it wasn't working. Stall-less ALU
ops now work better, to include grabbing the memory result as it comes out
of the memory unit and placing it straight into either ALU or memory unit
for the next instruction.
dgisselq 2679d 17h /zipcpu/
47 Added some new graphics, includes the file for the Zip Bones system. dgisselq 2679d 17h /zipcpu/
46 A series of updates associated with getting Dhrystone to work. Includes
updates to getting multiple files to link/work together within the assembler,
as well as getting quoted quotations to work in the lexer, and better
include file support in the preprocessor.
dgisselq 2679d 17h /zipcpu/
45 Library routines for 32-bit multiply and divide, both signed and unsigned. dgisselq 2679d 17h /zipcpu/
44 ?? dgisselq 2679d 17h /zipcpu/
43 Minor edits to the C++ testbench. dgisselq 2679d 17h /zipcpu/
42 Oops -- forgot to add the stack. dgisselq 2679d 17h /zipcpu/
41 Assembly file for the Dhrystone benchmark added. dgisselq 2679d 17h /zipcpu/
40 Quick update, updates the assembly for the new version of the assembler. dgisselq 2679d 17h /zipcpu/
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.
dgisselq 2682d 20h /zipcpu/
38 A couple of quick updates:

- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.

Documentation changes coming shortly.
dgisselq 2682d 22h /zipcpu/
37 Fixed some minor spelling errors. dgisselq 2691d 13h /zipcpu/
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.
dgisselq 2692d 01h /zipcpu/
35 I updated the system diagram to reflect the new version that has a direct
memory access controller, rather than the (useless) manual cache.
dgisselq 2708d 16h /zipcpu/
34 Bunches of changes, although very little changed with the core itself.

Regarding the core, some bugs were fixed within zipcpu.v (the CPU part of the
core), so that the debugger can change the program counter. The debugger
can now halt the CPU and then view, examine, and modify registers to include
the program counter, although live changes to the CC register have not been
tested.

There was also a bug in the stall handling of the wishbone bus delay line. This
has now been fixed.

Moving outwards to the system, some parameters have been added to zipsystem
to make it more configurable for whatever environment you might wish to place
it within. Other minor clean ups have taken place, mostly to the internal
documentation.

Lots of changes, though, to the assembler. The big one is the implementation
of #define macros, C style. Several buggy macros were in sys.i. These have
been fixed. The Makefile has been adjusted so that the build of test.S, which
depends upon sys.i, is now properly dependent upon sys.i for make purposes.
Further, not only will zpp, the assembler preprocessor, handle #define macros,
it will also recursive #defines. The assembler expression evaluator has also
been updated to properly handle both operator precedence, as well as modulo
arithmetic.

The master system test file, test.S, found in the sw/zasm directory has been
updated to reflect these new capabilities. (I really need to move it to the
bench/asm directory, so you may expect that change sometime later.)
dgisselq 2717d 20h /zipcpu/
33 Finally finished a first draft of the full specification! dgisselq 2720d 19h /zipcpu/
32 Updated the document to match the most recent changes to the CPU. Specifically,
these include the re-instatement of the full SUB command with immediate offset,
and ... others I cannot remember.

The new document also describes what conditions create pipeline stalls,
together with how many cycles each stall condition will create.
dgisselq 2721d 02h /zipcpu/

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.