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Rev Log message Author Age Path
92 Adjustments made to match the simplified early branching. dgisselq 3000d 06h /zipcpu/
91 Minor updates. dgisselq 3000d 06h /zipcpu/
90 Removed MOV x(PC),PC from the list of possible early branching instructions.
ADD X,PC and LDI X,PC are now the only recognized early branching instructions.
This was done to spare logic, although I don't think I spared more than a
LUT or two.
dgisselq 3000d 06h /zipcpu/
89 Minor changes, to include making default branching an ADD.[condition] X,PC
instruction, rather than allowing both MOV X(PC),PC and ADD X,PC instructions.

Further zopcodes.cpp contains several bug fixes.
dgisselq 3000d 06h /zipcpu/
88 Eliminated some warnings. The div fixes were to simplify the logic, even though
the result is less readable ...
dgisselq 3024d 06h /zipcpu/
87 Adjusted the operator input line to reflect actual logic inputs, rather
than the registered inputs which may have been out of date. (Indeed, they
were out of date for the bug I was chasing and fixed ...)
dgisselq 3026d 04h /zipcpu/
86 Removed the requirement to have the dev.scope.cpu hardware defined outside
of the Zip CPU (it was defined in another project). This was causing a bus
error in the simulator (which it should have), but taking it out fixes things
in the simulator (while removing capability from one special piece of H/W).
dgisselq 3026d 04h /zipcpu/
85 Minor update/correction to operand B definition. dgisselq 3026d 04h /zipcpu/
84 Minor updates. dgisselq 3026d 04h /zipcpu/
83 Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)

Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)

Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true.
dgisselq 3026d 04h /zipcpu/
82 Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line.
dgisselq 3026d 04h /zipcpu/
81 Trying to clean up ISE generated warnings. dgisselq 3026d 04h /zipcpu/
80 Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining.
dgisselq 3026d 04h /zipcpu/
79 Adjusted the opcodes for NOOP, BREAK, and LOCK. dgisselq 3030d 08h /zipcpu/
78 Found/corrected annoying bug in floating point documentation of the opcode
table.
dgisselq 3030d 08h /zipcpu/
77 First check-in: the test bench for the divide instruction. dgisselq 3031d 07h /zipcpu/
76 The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions.
dgisselq 3031d 07h /zipcpu/
75 Modified for VLIW instructions. dgisselq 3031d 07h /zipcpu/
74 Added a bunch of debugging code to the Dhrystone benchmark assembly file, as
well as two new testing assembly files.
dgisselq 3031d 07h /zipcpu/
73 Documentations updates. dgisselq 3031d 07h /zipcpu/

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