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[/] [zipcpu/] - Rev 99

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Rev	Log message	Author	Age	Path
79	Adjusted the opcodes for NOOP, BREAK, and LOCK.	dgisselq	3040d 05h	/zipcpu/
78	Found/corrected annoying bug in floating point documentation of the opcode table.	dgisselq	3040d 05h	/zipcpu/
77	First check-in: the test bench for the divide instruction.	dgisselq	3041d 04h	/zipcpu/
76	The biggest change here was to zippy_tb, to make it more similar to the debugger and to make it work with VLIW-type instructions.	dgisselq	3041d 04h	/zipcpu/
75	Modified for VLIW instructions.	dgisselq	3041d 04h	/zipcpu/
74	Added a bunch of debugging code to the Dhrystone benchmark assembly file, as well as two new testing assembly files.	dgisselq	3041d 04h	/zipcpu/
73	Documentations updates.	dgisselq	3041d 04h	/zipcpu/
72	Some updated graphics, now containing images of the CPU that include the divide and (currently non-existant) floating point unit.	dgisselq	3041d 04h	/zipcpu/
71	This contains a bunch of bug fixes. (A lot ...) For example, the pipeline stall code has also seriously changed, to fixed the pipeline memory load/op stage conflict, while maintaining no-stall operation for operands that don't need an offset. This had a cascading effect, however, so that the multiply could no longer complete in a single cycle. Therefore, the timing on the multiplies was slowed down to two cycles from a single cycle. (It's the only two-cycle ALU operation ...) The illegal instruction code has also been fixed, so that illegal instructions no longer stalls the prefetch bus.	dgisselq	3041d 04h	/zipcpu/
70	Updated the assembler support files, zopcodes in particular, to handle the disassembly of the new very long instruction word codes.	dgisselq	3041d 04h	/zipcpu/

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