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[/] [zipcpu/] [trunk/] - Rev 104

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84 Minor updates. dgisselq 3049d 10h /zipcpu/trunk
83 Added a flag to indicate whether an exception took place on the first
or second half of a VLIW instruction--will be zero in non-VLIW mode,
equivalent to the second half of the instruction having caused the
exception. (Expect these flags to be reordered some time in the future into
a less haphazard ordering ...)

Vastly simplified the pipeline logic, primarily for op_stall, but also touched
opA and opB. (Trying to fit within timing on Spartan 6 ...)

Changed division instruction to include a reset on clear_pipeline, to make
certain [BC $addr; DIV Rx,Ry ] works regardless of whether the condition is
true.		 dgisselq 3049d 10h /zipcpu/trunk
82 Found and (I hope) fixed a nasty bug that would send the prefetch into an
endless loop whenever you jumped to an instruction at the last location
in an unloaded cache line.		 dgisselq 3049d 10h /zipcpu/trunk
81 Trying to clean up ISE generated warnings. dgisselq 3049d 10h /zipcpu/trunk
80 Bug fix: declared the (combined) multiply to be signed again. Also
changed the name of the generate'd for block, to keep ISE from complaining.		 dgisselq 3049d 10h /zipcpu/trunk
79 Adjusted the opcodes for NOOP, BREAK, and LOCK. dgisselq 3053d 14h /zipcpu/trunk
78 Found/corrected annoying bug in floating point documentation of the opcode
table.		 dgisselq 3053d 14h /zipcpu/trunk
77 First check-in: the test bench for the divide instruction. dgisselq 3054d 13h /zipcpu/trunk
76 The biggest change here was to zippy_tb, to make it more similar to the debugger
and to make it work with VLIW-type instructions.		 dgisselq 3054d 13h /zipcpu/trunk
75 Modified for VLIW instructions. dgisselq 3054d 13h /zipcpu/trunk

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