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[/] [zipcpu/] [trunk/] [bench/] - Rev 20

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12 Bunch of changes while trying to get a hello world program:
1. Right shifts by 32 or more now result in zero, or all of the top bit in the
case of ASRs.
2. zdump now properly includes addresses with dumped lines.
3. zparser now properly handles immediate values via the .DAT instruction.
dgisselq 2626d 07h /zipcpu/trunk/bench/
11 This version works on an FPGA!!!

(Or at least the wdt.S program passes ...)
dgisselq 2626d 15h /zipcpu/trunk/bench/
10 Here's the watchdog timer code, as well as some pictures of the register
set.
dgisselq 2627d 05h /zipcpu/trunk/bench/
9 This checkin is the result of a watchdog timer test, and everything it took
to get the watchdog timer working. The timer function was simplified,
although it now uses a touch more resources--being able to count down 31
bits instead of 30. The parser was modified, since it couldn't handle
storing to register plus offsets like it was supposed to be able to. The
testbench, zippy_tb, was modified to accept an assembled machine code file
such as I might place on a board to test it.

Lots of work to get it working.

Looking at the files below, it looks like I'll need a second check in to check
in the watchdog timer test itself.
dgisselq 2627d 05h /zipcpu/trunk/bench/
8 Fixed the rotate left instruction to work in the zasm parser, and to be
properly referenced in the simulator. The instruction set documentation was
also adjusted to reflect what the CPU actually does.
dgisselq 2627d 11h /zipcpu/trunk/bench/
4 dgisselq 2627d 12h /zipcpu/trunk/bench/
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2628d 05h /zipcpu/trunk/bench/

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