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[/] [zipcpu/] [trunk/] [bench/] - Rev 30

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27 The big change to the test bench code in this directory is the support for
non-interactive operation. The test bench will now run in non-interactive
mode until either the CPU HALT's or executes a BUSY instruction. A 'HALT'
is deemed a test success, whereas a BUSY is deemed a test failure.

A usage() statement now informs the user what commands are available while
running the test bench interactively. (It looks a lot like the debugger looks
like, should you manage to get that up and running.)

The make file now also supports interactive and non-interactive testing via
the 'make itest' and 'make test' targets respectively.
dgisselq 2546d 07h /zipcpu/trunk/bench/
12 Bunch of changes while trying to get a hello world program:
1. Right shifts by 32 or more now result in zero, or all of the top bit in the
case of ASRs.
2. zdump now properly includes addresses with dumped lines.
3. zparser now properly handles immediate values via the .DAT instruction.
dgisselq 2570d 12h /zipcpu/trunk/bench/
11 This version works on an FPGA!!!

(Or at least the wdt.S program passes ...)
dgisselq 2570d 21h /zipcpu/trunk/bench/
10 Here's the watchdog timer code, as well as some pictures of the register
set.
dgisselq 2571d 10h /zipcpu/trunk/bench/
9 This checkin is the result of a watchdog timer test, and everything it took
to get the watchdog timer working. The timer function was simplified,
although it now uses a touch more resources--being able to count down 31
bits instead of 30. The parser was modified, since it couldn't handle
storing to register plus offsets like it was supposed to be able to. The
testbench, zippy_tb, was modified to accept an assembled machine code file
such as I might place on a board to test it.

Lots of work to get it working.

Looking at the files below, it looks like I'll need a second check in to check
in the watchdog timer test itself.
dgisselq 2571d 10h /zipcpu/trunk/bench/
8 Fixed the rotate left instruction to work in the zasm parser, and to be
properly referenced in the simulator. The instruction set documentation was
also adjusted to reflect what the CPU actually does.
dgisselq 2571d 17h /zipcpu/trunk/bench/
4 dgisselq 2571d 18h /zipcpu/trunk/bench/
2 An initial load. No promises of what works or not, but this is where the
project is at.
dgisselq 2572d 11h /zipcpu/trunk/bench/

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